- 產(chǎn)品詳情
CPLD MAX? 系列 600 門 32 宏電池 0.8um 技術(shù) 5V 28 引腳窗口 CDIP
CY7C344具有28引腳,300 mil DIP或加窗j引腳陶瓷芯片載體(HLCC),代表了該尺寸中密度最大的EPLD。8個(gè)專用輸入和16個(gè)雙向I/O引腳通信到一個(gè)邏輯陣列塊。在CY7C344 LAB中有32個(gè)宏細(xì)胞和64個(gè)膨脹產(chǎn)物項(xiàng)。當(dāng)使用I/O宏單元格作為輸入時(shí),使用兩個(gè)擴(kuò)展器來(lái)創(chuàng)建輸入路徑。即使所有的I/O引腳都由宏單元寄存器驅(qū)動(dòng),仍然有16個(gè)“埋藏”寄存器可用。所有輸入、宏單元和I/O引腳在LAB內(nèi)相互連接。
CY7C344的速度和密度使其成為所有類型應(yīng)用的自然選擇。僅使用這一個(gè)器件,設(shè)計(jì)人員就可以實(shí)現(xiàn)復(fù)雜的狀態(tài)機(jī)、注冊(cè)邏輯和組合“粘合”邏輯,而無(wú)需使用多個(gè)芯片。這種架構(gòu)靈活性允許CY7C344取代多芯片TTL解決方案,無(wú)論它們是同步的、異步的、組合的還是三者兼而有之。
特性
?高性能,高密度替代TTL,
74HC,以及自定義邏輯
?32個(gè)宏細(xì)胞,64個(gè)擴(kuò)增產(chǎn)物項(xiàng)在一個(gè)LAB中
?8個(gè)專用輸入,16個(gè)I/O引腳
?0.8微米雙金屬CMOS EPROM技術(shù)
?28引腳,300 mil DIP, cerDIP或28引腳HLCC, PLCC封裝
Product Technical Specifications
EU RoHS | Not Compliant |
ECCN (US) | 3A001.a.2.c |
Part Status | Obsolete |
HTS | 8542.39.00.01 |
Automotive | No |
PPAP | No |
Family Name | MAX? |
Program Memory Type | EPROM |
Number of Logic Blocks/Elements | 1 |
Number of Macro Cells | 32 |
Process Technology | 0.8um |
Device System Gates | 600 |
Data Gate | No |
Maximum Number of User I/Os | 16 |
Number of Flip Flops | 32 |
In-System Programmability | No |
Number of Inter Dielectric Layers | 2 |
Programmability | Yes |
Reprogrammability Support | No |
Maximum Internal Frequency (MHz) | 62.5 |
Maximum Clock to Output Delay (ns) | 15 |
Maximum Propagation Delay Time (ns) | 25 |
Speed Grade | 25 |
Individual Output Enable Control | No |
Minimum Operating Supply Voltage (V) | 4.5 |
Maximum Operating Supply Voltage (V) | 5.5 |
Typical Operating Supply Voltage (V) | 5 |
Maximum Operating Current (mA) | 220 |
Minimum Operating Temperature (°C) | -55 |
Maximum Operating Temperature (°C) | 125 |
Supplier Temperature Grade | Military |
Tradename | MAX |
Mounting | Through Hole |
Package Height | 3.56(Max) |
Package Width | 7.87(Max) |
Package Length | 37.72(Max) |
PCB changed | 28 |
Standard Package Name | DIP |
Supplier Package | Windowed CDIP |
Pin Count | 28 |
Lead Shape | Through Hole |